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| 74F164A Serial-In, Parallel-Out Shift Register October 1989 Revised August 1999 74F164A Serial-In, Parallel-Out Shift Register General Description The 74F164A is a high-speed 8-bit serial-in/parallel-out shift register. Serial data is entered through a 2-input AND gate synchronous with the LOW-to-HIGH transition of the clock. The device features an asynchronous Master Reset which clears the register, setting all outputs LOW independent of the clock. The 74F164A is a faster version of the 74F164. Features s Typical shift frequency of 90 MHz s Asynchronous Master Reset s Gated serial data input s Fully synchronous data transfers s 74F164A is a faster version of the 74F164 Ordering Code: Order Number 74F164ASC 74F164ASJ 74F164APC Package Number M14A M14D N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code. Logic Symbols Connection Diagram IEEE/IEC (c) 1999 Fairchild Semiconductor Corporation DS010613 www.fairchildsemi.com 74F164A Unit Loading/Fan Out Pin Names A, B CP MR Q0-Q7 Data Inputs Clock Pulse Input (Active Rising Edge) Master Reset Input (Active LOW) Outputs Description U.L. HIGH/LOW 1.0/1.0 1.0/1.0 1.0/1.0 50/33.3 Input IIH/IIL Output IOH/IOL 20 A/-0.6 mA 20 A/-0.6 mA 20 A/-0.6 mA -1 mA/20 mA Functional Description The 74F164A is an edge-triggered 8-bit shift register with serial data entry and an output from each of the eight stages. Data is entered serially through one of two inputs (A or B); either of these inputs can be used as an active HIGH Enable for data entry through the other input. An unused input must be tied HIGH. Each LOW-to-HIGH transition on the Clock (CP) input shifts data one place to the right and enters into Q0 the logical AND of the two data inputs (A * B) that existed before the rising clock edge. A LOW level on the Master Reset (MR) input overrides all other inputs and clears the register asynchronously, forcing all Q outputs LOW. Mode Select Table Operating Mode Reset (Clear) Shift MR L H H H H Inputs A X l l h h B X l h l h Outputs Q0 L L L L H Q1-Q7 L-L q0-q6 q0-q6 q0-q6 q0-q6 H(h) = HIGH Voltage Levels L(l) = LOW Voltage Levels X = Immaterial qn = Lower case letters indicate the state of the referenced input or output one setup time prior to the LOW-to-HIGH clock transition. Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 74F164A Absolute Maximum Ratings(Note 1) Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 1) Input Current (Note 1) Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output 3-STATE Output Current Applied to Output in LOW State (Max) ESD Last Passing Voltage (Min) twice the rated IOL (mA) 4000V -0.5V to VCC -0.5V to +5.5V -65C to +150C -55C to +125C -55C to +150C -0.5V to +7.0V -0.5V to +7.0V -30 mA to +5.0 mA Recommended Operating Conditions Free Air Ambient Temperature Supply Voltage 0C to +70C +4.5V to +5.5V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol VIH VIL VCD VOH VOL IIH IBVI ICEX VID IOD IIL IOS ICC Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Output HIGH Leakage Current Input Leakage Test Output Leakage Circuit Current Input LOW Current Output Short-Circuit Current Power Supply Current -60 35 4.75 3.75 -0.6 -150 55 10% VCC 5% VCC 10% VCC 2.5 2.7 0.5 5.0 7.0 50 Min 2.0 0.8 -1.2 Typ Max Units V V V V V A A A V A mA mA mA Min Min Min Max Max Max 0.0 0.0 Max Max Max VCC Conditions Recognized as a HIGH Signal Recognized as a LOW Signal IIN = -18 mA IOH = -1 mA IOH = -1 mA IOL = 20 mA VIN = 2.7V VIN = 7.0V VOUT = VCC IID = 1.9 A All other pins grounded VIOD = 150 mV All other pins grounded VIN = 0.5V VOUT = 0V CP = HIGH MR = GND, A, B = GND 3 www.fairchildsemi.com 74F164A AC Electrical Characteristics TA = +25C Symbol Parameter Min fMAX tPLH tPHL tPHL Maximum Clock Frequency Propagation Delay CP to Qn Propagation Delay MR to Qn 80 3.0 3.5 5.0 VCC = +5.0V CL = 50 pF Typ 120 4.8 5.0 7.0 7.5 8.0 10.0 Max TA = -55C to +125C VCC = 5.0V CL = 50 pF Min 60 2.5 3.0 4.0 9.0 8.5 12.5 Max TA = 0C to +70C VCC = 5.0V CL = 50 pF Min 80 3.0 3.5 5.0 7.5 8.0 10.5 Max MHz ns ns Units AC Operating Requirements TA = +25C Symbol Parameter VCC = +5.0V Min tS(H) tS(L) tH(H) tH(L) tW(H) tW(L) tW(L) tREC Setup Time, HIGH or LOW A or B to CP Hold Time, HIGH or LOW A or B to CP CP Pulse Width HIGH or LOW MR Pulse Width, LOW Recovery Time MR to CP 4.5 4.0 1.0 1.0 4.0 7.0 4.0 5.0 Max TA = -55C to +125C VCC = 5.0V Min 5.5 4.0 1.0 1.0 4.0 7.0 5.0 6.5 Max TA = 0C to +70C VCC = 5.0V Min 4.5 4.0 1.0 1.0 4.0 7.0 4.0 5.0 ns ns ns ns Max Units www.fairchildsemi.com 4 74F164A Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow Package Number M14A 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D 5 www.fairchildsemi.com 74F164A Serial-In, Parallel-Out Shift Register Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N14A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 6 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com |
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